HAD TT: One Gate on a Real Chip
Tiny Tapeout makes it easier and cheaper to get a digital design manufactured on a real chip. I used it at a Hackaday Supercon 2025 workshop. It was a fun learning experience: engineering and designing code and logic that gets imprinted onto a small chip. The likelihood of that design landing on a production chip is low. It is still an awesome experience.
The repo is ttsky-wokwi-template. The drawing lives in Wokwi, under the name Lou First Template. If you want the same path, start with Tiny Tapeout’s own notes: the FAQ, the digital design lessons, SiliWiz for how a semiconductor is actually made, and the guide to building the files on your own machine.
Where It Landed
The submission is named HAD TT. The author on the shuttle is iSD. It is address 289 on Tiny Tapeout SKY 25b. The project page is 289 HAD TT.
The shuttle closed on November 10, 2025, with 316 designs. It went to ChipFoundry’s CI-2511 shuttle on the SkyWater 130nm open source process. Tiny Tapeout lists chips expected on July 14, 2026, and estimated shipping on August 30, 2026, chip list. I have not found a delivery confirmation on the chip page, so I will not pretend the package has shown up.
The repo was created on October 31, 2025, nine days before the shuttle closed. Other Supercon 2025 workshop designs are on the same chip. HAD TT is one of them.
The Bit & Bytes
What does the design actually do? One thing. It ANDs two inputs.
Chip input 0 goes to the gate’s A pin. Chip input 1 goes to B. The output wire splits and lands on chip outputs 3, 4 and 5. Both inputs have to be on before those outputs come on. If either input is off, all three stay off. There is no second function hiding in the repo.
That is the truth table:
- IN0 off, IN1 off: outputs off
- IN0 off, IN1 on: outputs off
- IN0 on, IN1 off: outputs off
- IN0 on, IN1 on: outputs on
The rest of the Wokwi page is the workshop template. A row of switches, a clock, a step button, a reset, and a 7-segment display were already there. The AND gate is the part I added.
There is one extra set of wires I would not defend as a feature. Outputs 3, 4 and 5 are also tied to the Step button. It is in the drawing. A later pass should decide whether those wires stay.
The datasheet names do not match the wires. In info.yaml I labeled output 0 “t1 and” and output 1 “t1 and 2”. The gate drives outputs 3, 4 and 5. If the pin table and the drawing disagree, trust the drawing.
The clock is a similar story. An AND gate does not use one. info.yaml still declares 10,000 Hz, because the template asks for a clock frequency. The clock part in Wokwi is set to 100, and that number is only the on-screen simulation. The gate ignores both.
The repo does not hold the drawing. info.yaml holds the Wokwi project id, 446363984157070337, which is the long number in the project URL. The GitHub action fetches the netlist from Wokwi and builds the ASIC files.
src/cells.v is the template’s translation of a Wokwi AND into Verilog. I did not write that file. It shipped with the template, and it is the line this gate becomes:
assign out = a & b;
a and b are the two inputs. out is their AND. That is the whole mapping.
The design takes one tile. The template says a single tile is about 167 by 108 micrometers. The GDS viewer counts 1,727 cell instances. Almost all of them are filler, the cells that pad an empty tile. The logic is one sky130_fd_sc_hd__and2_1. That is SkyWater’s 2-input AND, and it matches the drawing.
The datasheet text is still the workshop draft. “It works.” “We just run it.” “Can be anything.” Fine for a Saturday. Not fine if someone asks how to test it. The test is the truth table above: set the two inputs, and watch outputs 3, 4 and 5.
What the Actions Did
On October 31, 2025 the actions were red for about sixteen minutes, then green. GitHub no longer has those logs, so I cannot quote the error. What I can quote is the commit history, and which run went green.
- 21:31 UTC. Template, and
wokwi_idstill 0. Failed. - 21:36. Wokwi id filled in, title HAD_TT, author iSD, description “Logic gates.” Failed.
- 21:39. Datasheet set to “It works” and “We just run it.” Failed.
- 21:42. Clock set from 0 to 10,000 Hz. Failed.
- 21:44. Title changed from HAD_TT to HAD TT. Failed.
- 21:45. External hardware set to “Can be anything.” Failed.
- 21:48. Outputs named “t1 and” and “t1 and 2”. Passed.
The first green run is 8c3fe47. I will not claim the pin names were the fix. They are the last edit before gds, docs and wokwi_test passed. On October 18, 2026 a Dependabot bump of pytest went through, and the same three workflows passed again.
If your own action dies on the Pages step, Tiny Tapeout’s FAQ has the usual cause: GitHub Pages is not enabled. I cannot prove that was this failure. The log is gone.
Closing Bytes
One AND gate. Three outputs. A tile on a shuttle with 315 neighbors. HAD TT is not going into a phone, and I would still do the workshop again.
The lessons are the plain ones:
- A blank template fails on purpose. Fill in the Wokwi id before you expect a green check.
- Name the pins to match the wires. The datasheet and the drawing still disagree.
- Write the error down while the log is still there. GitHub threw these ones away.
- One gate is enough to finish. The interesting part was the path from a drawing to a GDS file.
I am attending the Tiny Tapeout workshop again at Hackaday Supercon 2026. Pat Deegan is leading it. Same idea: draw a design, simulate it, and generate the files for the Sky130 process, with the option to submit to the next shuttle. When the design is ready, the submission portal is where it goes for purchase availability.
